Recessed chip MCM packages are gaining acceptance in IC device interconnection technology because of efficient utilization of interconnect substrate area, low overall package profile, and reduced interconnection length. A variety of recessed chip package options are described and claimed in U.S. Pat. No. 5,608,262, issued Mar. 4, 1997 which, for purposes of this disclosure, is incorporated herein by reference.
Recessed chip packages are characterized by three components, a primary IC chip, defined for the purpose of this exposition as a first level component, an intermediate interconnection substrate (IIS) which may be either an IC chip or a passive interconnection substrate, defined here as a second level component, and a system interconnection substrate (SIS) which is typically a printed circuit board (PCB) and defined as a third level component. These components are progressively larger in area so that the second level component(s) can support one or more IC chips, and the third level components can accommodate one or more second level components. In a three component package, the first level components are typically flip-chip bonded to the second level components, and the second level components are flip-chip mounted on the third level component with the first level components recessed into cavities formed in the third level component.
A number of variations using this basic concept are possible, e.g. the system interconnection substrate can itself function as an intermediate interconnection substrate and attach to a fourth board level, with the second level components recessed into cavities in the fourth level component.
Recessed cavity structures have efficient interconnection arrangements, but there is an ever growing need for denser interconnections and higher interconnection performance.